Due to the high resource requirements of extreme ultraviolet (EUV) lithography, 193 nm immersion lithography remains an attractive alternative for the fabrication of 20 nm and beyond technology nodes. However, 193 nm immersion lithography techniques suffer from reliability and yield issues caused by time dependent dielectric breakdown (TDDB), especially for tight contact tip-to-tip spacing. The problems caused by tight tip-to-tip contact spacing are particularly severe in highly integrated circuits with the greatest demands for feature size reduction and scaling (e.g., 10 nm SRAM design).
FIG. 1 illustrates a top view 100 of contact trenches 101 and gates 103. Due to the tight contact to gate pitch (CGP) 105, a triple patterning process (e.g., with 193 nm immersion lithography) is used to pattern the contact trenches 101 alongside the gates 103. Despite the high resolution of the triple patterning process, shorts may still occur in tight tip-to-tip contact spacings. For example, the tip-to-tip spacing near gate contacts 109 may be particularly small. Furthermore, process optimization for triple patterning is particularly expensive and resource-intensive because of the unknown variation of the tools at these feature sizes. For example, product overlay does not scale at the same rate as the rate at which chip features are down-scaled. The integration margin for 20 nm nodes is, therefore, not as great as it is for less advanced technology nodes. In addition, mask error remains a problem and further complicates the contact integration process. For example, the risk of contact-to-contact shorts is greater for end-of-line process stages because of the greater mask error enhancement factor (MEEF).
A need therefore exists for a methodology enabling less costly middle-of-line (MOL) contact integration with improved yield and reliability, and the resulting device.